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DATA SHEET
PCF8549 65 x 102 pixels matrix LCD driver
Product specification File under Integrated Circuits, IC12 1997 Nov 21
Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
FEATURES * Single chip LCD controller/driver * 65 row and 102 column outputs * Display data RAM 65 x 102 bits * On-chip: - Generation of LCD supply voltage - Generation of intermediate LCD bias voltages - Oscillator requires no external components (external clock also possible) * 400 kHz Fast I2C Interface * CMOS compatible inputs * Mux rate: 65 * Logic supply voltage range VDD1 - VSS: 1.5 to 6 V * Voltage generator voltage range VDD2/2_HV - VSS: 2.4 to 5 V * Display supply voltage range VLCD - VSS: 7.0 to 16 V * Low power consumption, suitable for battery operated systems * Temperature compensation of VLCD * Interlacing for better display quality * Slim chip layout, suited for chip-on-glass applications. APPLICATIONS * Telecom equipment * Portable instruments * Point of sale terminals. ORDERING INFORMATION PACKAGE TYPE NUMBER NAME PCF8549U/2/F1 TRAY chip with bumps in tray DESCRIPTION GENERAL DESCRIPTION
PCF8549
The PCF8549 is a low power CMOS LCD controller driver, designed to drive a graphic display of 65 rows and 102 columns. All necessary functions for the display are provided in a single chip, including on-chip generation of LCD supply and bias voltages, resulting in a minimum of external components and low power consumption. The PCF8549 interfaces to most microcontrollers via an I2C interface. Packages The PCF8549U/2 is available as bumped die. Sawn wafer as chip sorted in chip tray. For further details see Section "Bonding pads". Customized TCP upon request.
VERSION
1997 Nov 21
2
Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
BLOCK DIAGRAM
PCF8549
C0 to C101
R0 to R64
COLUMN DRIVERS
ROW DRIVERS
DATA LATCHES VLCD2 Bias voltage generator
SHIFT REGISTER
OSCILLATOR VLCD1 HVGEN 7 stages Dual Ported RAM 65x102 Bit TIMING GENERATOR
OSC
IIC INTERFACE
DISPLAY CONTROL LOGIC
Fig.1 Block diagram.
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VDD1 VDD2 VDD2_HV VSS1 VSS2 VSS2_HV
SDA_out SDA SCL
RES
SA0
T1 T2 T3 T4 T5
T6 T7
Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
PINNING SYMBOL R0 to R64 C0 to C101 VSS1,2,2_HV VDD1,2,2_HV VLCD1,2 T1 T2 T3 T4 T5 T6 T7 SDA SCL SDA_OUT SA0 OSC RES Pin functions R0 TO R64: ROW DRIVER OUTPUTS These pads output the row signals. C0 TO C101: COLUMN DRIVER OUTPUTS These pads output the column signals. VSS1,2,2_HV: NEGATIVE POWER SUPPLY RAILS Negative power supplies. VDD1,2,2_HV: POSITIVE POWER SUPPLY RAILS DESCRIPTION LCD row driver outputs LCD column driver outputs negative power supply supply voltage LCD supply voltage test 1 input test 2 output test 3 I/O test 4 I/O test 5 input test 6 input test 7 input I2C data input I2C clock line I2C output least significant bit of slave address oscillator external reset input, low active
PCF8549
VDD2 and VDD2_HV are the supply voltages for the internal voltage generator. Both have to be on the same voltage and may be connected together outside of the chip. If the internal voltage generator is not used, they should be both connected to ground. VDD1 is used as power supply for the rest of the chip. This voltage can be a different voltage than VDD2 and VDD2_HV. VLCD1,2: LCD POWER SUPPLY Positive power supply for the liquid crystal display. If the internal voltage generator is used, the two supply rails VLCD1 and VLCD2 must be connected together. An external LCD supply voltage can be supplied using the V pad. In this case, VLCD1 has to be connected to ground, and the internal voltage generator has to be programmed to zero. If the PCF8549 is in power-down mode, the external LCD supply voltage has to be switched off.
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Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
T1, T2, T3, T4, T5, T6 AND T7: TEST PADS T1, T3, T4, T5, T6 and T7 must be connected to VSS1, T2 is to be left open. Not accessible to user. SDA/SDA_OUT: I2C DATA LINES Output and input are separated. If both pads are connected together they behave like a standard I2C pad. SCL: I2C CLOCK SIGNAL Input for the I2C-bus clock signal. FUNCTIONAL DESCRIPTION Block diagram functions OSCILLATOR
PCF8549
The on-chip oscillator provides the clock signal for the display system. No external components are required and the OSC input must be connected to VDD1. An external clock signal, if used, is connected to this input. I2C INTERFACE The I2C interface receives and executes the commands sent via the I2C-bus. It also receives RAM-data and sends them to the RAM. During read access the 8-bit parallel data or the status register content is converted to a serial data stream and output via the I2C-bus. DISPLAY CONTROL LOGIC
SA0: SLAVE ADDRESS With the SA0 pin two different slave addresses can be selected. That allows to connect two PCF8549 LCD drivers to the same I2C-bus. OSC: OSCILLATOR When the on-chip oscillator is used this input must be connected to VDD1. An external clock signal, if used, is connected to this input. RES: RESET This signal will reset the device. Signal is active low.
The display control logic generates the control signals to read out the RAM via the 101 bit parallel port. It also generates the control signals for the row, and column drivers. DISPLAY DATA RAM (DDRAM) The PCF8549 contains a 65 x 102 bit static RAM which stores the display data. The RAM is divided into 8 banks of 102 bytes and one bank of 102 bits ((8 x 8 + 1) x 102 bits). During RAM access, data is transferred to the RAM via the I2C interface. There is a direct correspondence between X-address and column output number. TIMING GENERATOR The timing generator produces the various signals required to drive the internal circuitry. Internal chip operation is not disturbed by operations on the I2C-bus. LCD ROW AND COLUMN DRIVERS The PCF8549 contains 65 row and 102 column drivers, which connect the appropriate LCD bias voltages to the display in accordance with the data to be displayed. Figure 2 shows typical waveforms. Unused outputs should be left unconnected.
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Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
PCF8549
frame n
frame n+1
Vstate1(t) Vstate2(t)
ROW 0 R0 (t)
VLCD V2 V3 V4 V5 VSS VLCD V2 V3 V4 V5 VSS VLCD V2 V3 V4 V5 VSS VLCD V2 V3 V4 V5 VSS
ROW 2 R2 (t)
COL 0 C0 (t)
COL 1 C1 (t)
VLCD V3 Vstate1(t) VLCD - V2 0V V 3 - V2 V4 - V5 0V V5 V4 - VLCD - VLCD VLCD V3 Vstate2(t) VLCD - V2 0V V 3 - V2 V4 - V5 0V V5 V4 - VLCD - VLCD
... 63
0 2 4 6 8 10 ...
... 64 1 3 5 7 9 ...
... 63 0 2 4 6 8 10 ...
... 64 1 3 5 7 9 ...
VSS=0V
Vstate1(t) = C1(t) - R0(t) Vstate2(t) = C1(t) - R2(t)
Fig.2 Typical LCD driver waveforms.
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Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
PCF8549
DDRAM bank 0
bank 1
bank 2
bank 3
bank 7
bank 8
Fig.3 DDRAM to display mapping.
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Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
Addressing The Display data RAM of the PCF8549 is accessed as indicated in Figs 3, 4, 4, 6 and 7. The display RAM has a matrix of 65 x 102 bits. The columns are addressed by the address pointer. The address ranges are: X 0 to 101 (1100101b) and Y 0 to 8 (1000b). Addresses outside these ranges are not allowed. In vertical addressing mode (V = 1) the Y address increments (see Fig.7) after each byte. After the last Y address (Y = 8) Y wraps around to 0 and X increments to address the next column. In horizontal addressing mode (V = 0) the X address increments (see Fig.6) after each byte. After the last X address (X = 101) X wraps around to 0 and Y increments to address the next row. After the very last address (X = 101 and Y = 8) the address pointers wrap around to address (X = 0 and Y = 0).
PCF8549
The MX bit allows a horizontal mirroring: When MX = 1, the X address space is mirrored: The address X = 0 is then located at the right side (column 101) of the display (see Fig.4). When MX = 0 the mirroring is disabled and the address X = 0 is located at the left side (column 0) of the display (see Fig.4). If the RM-bit (read-modify-write mode) is set, the address is only incremented after a write, otherwise the address is incremented after both read and write access to the display data RAM.
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Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
DISPLAY DATA RAM STRUCTURE
PCF8549
MSB
0
LSB
MSB
8
LSB
0
X-address Y-address
101
Fig.4 RAM format, addressing (MX = 0).
MSB
0
LSB
MSB
8
LSB
101
X-address Y-address
0
Fig.5 RAM format, addressing (MX = 1).
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Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
PCF8549
0
1
2
0
102 103 104 204 205 206 306 307 308 408 409 410 510 511 512 612 613 614 714 715 716 816 817 818 917
Y-address
8
0 X-address
101
Fig.6 Sequence of writing data bytes into RAM with horizontal addressing (V = 0).
0 1 2 3 4 5 6 7 8
9 10
0
Y-address
917
8
0
101
Fig.7 Sequence of writing data bytes into RAM with vertical addressing (V = 1).
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Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
RAM access If the D/C bit is 1 the RAM can be accessed in both read and write access mode, depending on the R/W bit. The data is written to the RAM during the acknowledge cycle.
PCF8549
period of the clock pulse as changes in the data line at this time will be interpreted as a control signal. START AND STOP CONDITIONS (see Fig.10) Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P). SYSTEM CONFIGURATION (see Fig.11)
Set Address
Set Read Modify Write Mode
* Transmitter: The device which sends the data to the bus * Receiver: The device which receives the data from the bus
Read Data
* Master: The device which initiates a transfer, generates clock signals and terminates a transfer * Slave: The device addressed by a master * Multi-Master: More than one master can attempt to control the bus at the same time without corrupting the message * Arbitration: Procedure to ensure that, if more than one master simultaneously tries to control the bus, only one is allowed to do so and the message is not corrupted
Write Data
no
Finished?
* Synchronisation: Procedure to synchronize the clock signals of two or more devices. ACKNOWLEDGE (see Fig.12) Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a stop condition.
yes END
Fig.8 Read modify write access.
I2C-BUS INTERFACE Characteristics of the I2C-bus The I2C-bus is for bi-directional, two-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only when the bus is not busy. BIT TRANSFER (see Fig.9) One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH
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Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
PCF8549
SDA
SCL data line stable; data valid change of data allowed
MBC621
Fig.9 Bit transfer.
SDA
SDA
SCL S START condition P STOP condition
SCL
MBC622
Fig.10 Definition of start and stop conditions.
MASTER TRANSMITTER/ RECEIVER SDA SCL
SLAVE RECEIVER
SLAVE TRANSMITTER/ RECEIVER
MASTER TRANSMITTER
MASTER TRANSMITTER/ RECEIVER
MGA807
Fig.11 System configuration.
DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER S START CONDITION
MBC602
1
2
8
9
clock pulse for acknowledgement
Fig.12 Acknowledgement on the I2C-bus.
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Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
I2C-bus protocol The PCF8549 supports both read and write access. The R/W bit is part of the slave address. Before any data is transmitted on the I2C-bus, the device which should respond is addressed first. Two 7-bit slave addresses (0111100 and 0111101) are reserved for the PCF8549. The least significant bit of the slave address is set by connecting the input SA0 to either logic 0 (VSS1) or 1 (VDD1). The I2C-bus protocol is illustrated in Fig.13. The sequence is initiated with a START condition (S) from the I2C-bus master which is followed by the slave address. All slaves with the corresponding address acknowledge in parallel, all the others will ignore the I2C-bus transfer. After acknowledgement, one or more command words follow which define the status of the addressed slaves. A command word consists of a control byte, which defines Co and D/C, plus a data byte (see Fig.13 and Table 1). The last control byte is tagged with a cleared most significant bit, the continuation bit Co. After a control byte with a cleared Co-bit, only data bytes will follow. The state
PCF8549
of the D/C-bit defines whether the data-byte is interpreted as a command or as RAM-data.The control and data bytes are also acknowledged by all addressed slaves on the bus. After the last control byte, depending on the D/C bit setting, either a series of display data bytes or command data bytes may follow. If the D/C bit was set to `1', these display bytes are stored in the display RAM at the address specified by the data pointer. The data pointer is automatically updated and the data is directed to the intended PCF8549 device. If the D/C bit of the last control byte was set to `0', these command bytes will be decoded and the setting of the device will be changed according to the received commands. The acknowledgement after each byte is made only by the addressed slave. At the end of the transmission the I2C-bus master issues a stop condition (P). If the R/W bit is set to one in the slave-address, the chip will output data immediately after the slave-address according to the D/C bit, which was sent during the last write access. If no acknowledge is generated by the master after a byte, the driver stops transferring data to the master.
acknowledgement from PCF8549
acknowledgement from PCF8549
acknowledgement from PCF8549
acknowledgement from PCF8549
acknowledgement from PCF8549
S 0 1 1 1 1 0 A 0 A 1 DC
0
S
control byte
A
data byte
A 0 DC
control byte
A
data byte
AP
slave address
Co
2n > 0 bytes
Co
1 byte
n > 0 bytes MSB................. LSB
acknowledgement from Master
acknowledgement from Master
acknowledgement from Master
acknowledgement from Master
S01 1110A1A
0
S
data byte
A
data byte
A
data byte
A
data byte
AP
slave address
S 0 1 1 1 1 0 AR 0W
CO DC 0 0
0
000
A
PCF8549 slave address
Control Byte
Fig.13 I2C-bus protocol.
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Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
INSTRUCTIONS
PCF8549
The instruction format is divided into two modes: If D/C is set low, the status byte can be read or commands can be sent to the chip, depending on the R/W signal. If D/C is set high, the DDRAM will be accessed. Every instruction can be sent in any order to the PCF8549. Table 1 Instruction set COMMAND BYTE INSTRUCTION H = 0 or 1
NOP Function Set Read Status Byte Write Data Read Data 0 0 0 1 1 0 0 1 0 1 0 0 0 0 X D6 D6 0 1 X D5 D5 0 MX D D4 D4 0 MY E D3 D3 0 PD MX D2 D2 0 V MY D1 D1 0 H X D0 D0 no operation power down control; entry mode; Extended Instruction Set control (H) reads status byte writes data to RAM reads data from RAM
D/C
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DESCRIPTION
PD D7 D7
0 0 0 0 0 1
H=0
Set Read Modify Write Reserved Display Control Reserved Set Y address of RAM Set X address of RAM. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 X6 0 0 0 0 0 X5 0 0 0 1 0 X4 0 0 1 X Y3 X3 0 1 D X Y2 X2 1 X 0 X Y1 X1 RM X E X Y0 X0 sets the read-modify-write mode do not use sets display configuration do not use sets Y-address of RAM: 0 Y 8 sets X-address of RAM: 0 X 101
H=1
Reserved Reserved Reserved Bias System Reserved Set VOP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 VOP6 0 0 0 0 0 X VOP5 0 0 0 0 1 X VOP4 0 0 0 1 0 X VOP3 0 0 1 X BS2 X VOP2 0 1 TC1 X BS1 X VOP1 1 X TC0 X BS0 X VOP0 do not use do not use set temperature coefficient (TCx) do not use Set Bias System(BSx) do not use (reserved for test...) write VOP to register
Temperature Control 0
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Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
Table 2 Explanations for symbols in Table 1 BIT PD V H MX MY RM D and E 00 10 01 11 TC[1 : 0] 00 01 10 11 BS[2 : 0] chip is active horizontal addressing use basic instruction set normal X-addressing display is not vertically mirrored display blank normal mode all display segments on inverse video mode VLCD temperature coefficient 0 VLCD temperature coefficient 1 VLCD temperature coefficient 2 VLCD temperature coefficient 3 bias system 0 1 chip is in power down mode vertical addressing use extended instruction set X-address is mirrored display is vertically mirrored 1 0 0 0 0 D=0 E=0
PCF8549
RESET STATE
read-modify-write mode is disabled read-modify-write mode is enabled 0
TC[1 : 0] = 00
BS[2 : 0] = 000
External reset (RES) After power-on a reset pulse has to be applied immediately to the chip, as it is in an undefined state. A reset of the chip can be achieved with the external reset pin. After the reset the LCD driver is set to the following status: * Power down mode (PD = 1) * All LCD-outputs at VSS (display off) * Read-modify-write mode is disabled (RM = 0) * Horizontal addressing (V = 0) * Normal instruction set (H = 0) * Normal display (MX = MY = 0) * Display blank (E = D = 0) * Address counter X[6 : 0] = 0 and Y[3 : 0] = 0 * Temperature coefficient (TC[1 : 0] = 0) * Bias system (BS[2 : 0] = 0) * Read-modify-write mode disabled (RM = 0) * VLCD is equal to 0, the HV generator is switched off (VOP[6 : 0] = 0) * After power-on, RAM data are undefined; The reset signal does not change the content of the RAM. Set read-modify-write When RM = 0, the read-modify-write mode is disabled. The X/Y-address counter is incremented after every read or write access to the display data RAM. When RM = 1, the read-modify-write mode is enabled. In this mode the X/Y-address is incremented only after a write access to the display data RAM. The X/Y-address will not be incremented after a read access to the RAM.
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Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
Function Set PD (POWER DOWN) * All LCD outputs at VSS (display off) * Bias generator and VLCD generator off * Oscillator off (external clock possible) * VLCD can be disconnected * Parallel bus, command, etc. function * RAM contents not cleared; RAM data can be written. V When V = 0, the horizontal addressing is selected. The data is written into the RAM as shown in Fig.6. When V = 1, the vertical addressing is selected. The data is written into the RAM as shown in Fig.7. H When H = 0 the commands `display control', `set Y address' and `set X address' can be performed, when H = 1 the other commands can be executed. The commands `write data' and `function set' can be executed in both cases. Table 3 X-/Y-Address range CONTENT bank 0 (display RAM) bank 1 (display RAM) bank 2 (display RAM) bank 3 (display RAM) bank 4 (display RAM) bank 5 (display RAM) bank 6 (display RAM) bank 7 (display RAM) bank 8 (display RAM) 0 to 101 0 to 101 0 to 101 0 to 101 0 to 101 0 to 101 0 to 101 0 to 101 0 to 101 MX
PCF8549
When MX = 0, the display is written from left to right (X = 0 is on the left side, X = 100 is on the right side of the display). When MX = 1 the display is written from right to left (X = 0 is on the right side, X = 100 is on the left side of the display). MY When MY = 1, the display is mirrored vertically. Display Control D AND E The bits D and E select the display mode (see Table 2). Set Y address of RAM Y[3 : 0] defines the Y address vector address of the RAM.
YYYY 3 210 0000 0001 0010 0011 0100 0101 0110 0111 1000
ALLOWED X-RANGE
In bank 8 only the MSB is accessed. Set X address of RAM The X address points to the columns. The range of X is 0 to 101(65 hex). Temperature Control Due to the temperature dependency of the liquid crystals viscosity the LCD controlling voltage VLCD must be increased with lower temperature to maintain optimal contrast. There are 4 different temperature coefficients available in the
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Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
PCF8549
PCF8549 (see Fig.14). The coefficients are selected by the two bits TC[1 : 0]. Table 6 shows the typical values of the different temperature coefficients. The coefficients are proportional to the programmed VLCD.
VLCD
16oC(typ)
temperature
Fig.14 Temperature coefficients.
Bias value: 1 The bias voltage levels are set in the ratio of R - R - nR - R - R giving a ------------ bias system. The resulting bias levels n+4 are shown in table 5. Different multiplex rates require different factors n (see Table 4). This is programmed by BS[2 : 0]. For MUX 1 : 65 the optimum bias value n is given by: n = resulting in 19bias. Table 4 BS[2] 0 0 0 0 1 Programming the required Bias system BS[1] 0 0 1 1 0 BS[0] 0 1 0 1 0 n 7 6 5 4 3 b (RES. COUNT) 11 10 9 8 7 MUX RATE 1 : 100 1 : 81 1 : 64 1 : 49 1 : 36 m-3 = 65 - 3 = 5.06 = 5
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Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
BS[2] 1 1 1 BS[1] 0 1 1 BS[0] 1 0 1 n 2 1 0 b (RES. COUNT) 6 5 4
PCF8549
MUX RATE 1 : 24 1 : 16 1:9
Table 5
LCD bias voltage BIAS VOLTAGES VLCD (b-1)/b x VLCD (b-2)/b x VLCD 2/b x VLCD 1/b x VLCD VSS
SYMBOL V1 V2 V3 V4 V5 V6 Set VOP value:
The operation voltage VLCD can be set by software. The generated voltage is dependent of the temperature, the programmed temperature coefficient (TC), and the programmed voltage at reference temperature (TCUT). (1) V LCD = ( a + VOP b ) + ( T - T CUT ) TC The voltage at reference temperature (VLCD(T=TCUT)) can be calculated as: (2) V LCD = ( a + VOP b ) The parameters are explained in table 6. The maximum voltage that can be generated is depending on the VDD2/2_HV Voltage and the display load current. The relation ship is shown in Fig.16. The charge pump is turned off if Vop[6 : 0] is set to zero. For Mux 1 : 65 the optimum operation voltage of the liquid can be calculated as: 1 + 65 V LCD = -------------------------------------- V th = 6.85 V th 1 2 1 - ---------- 65 where Vth is the threshold voltage of the liquid crystal material used.
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Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
PCF8549
VLCD
b
a
00 01 02 03 04 05 06 07 08 09 0A ... VOP[6:0] (programmed) [00 hex ... 7F hex]
Fig.15 VOP programming of PCF8549. Table 6 Typical values for parameters for the HV-Generator programming VALUE 7.06 0.06 16 00 - 0.142 10 01 - 1.3 10 10 - 2.467 10 11 - 3.483 10
-3 -3 -3 -3
SYMBOL a b TCUT TC
UNIT V V
0C
V/oC V LCD ( T = T CUT ) V/oC V LCD ( T = T CUT ) V/oC V LCD ( T = T CUT ) V/oC V LCD ( T = T CUT )
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Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
LIMITING VALUES
PCF8549
In accordance with the Absolute Maximum System (IEC 134); all voltages referred to VSS = 0V unless otherwise specified.
SYMBOL VDD VLCD ISS Vi/VO VOLCD Ii Io PTOT PO TAMB TSTG Notes
PARAMETER supply voltage range supply voltage range LCD supply current input/output voltage range LCD output voltage range DC input current DC output current power dissipation per package power dissipation per output operating ambient temperature. range storage temperature range
MIN -0.5 -0.5 -50 -0.5 -0.5 -10 -10 -40 -65
MAX +7 +17 50 VDD+0.5 VLCD+0.5 10 10 300 50 +85 +150
UNIT V V mA V V mA mA mW mW C C
1. Stresses above those listed under Limiting Values may cause permanent damage to the device. 2. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. 3. with external LCD supply voltage external supplied (voltage generator disabled). VDDmax (VDD2,VDD2_HV) is 5V if LCD supply voltage is internally generated (voltage generator enabled). HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices (see "Handling MOS Devices"). The PCF8549 withstands the following stress: * approximately 1.0kV Human Body Model * approximately 150V Machine Model
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Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
DC CHARACTERISTICS Table 7
PCF8549
VDD1 = 1.5 to 6 V; VDD2/2_HV = 2.4 to 5.0 V; VDD2 = VDD2_HV; VSS1 = VSS2 = VSS2_HV = 0 V; VLCD = 7 to 16 V; Tamb = -40 to +85 C; unless otherwise specified. PARAMETER Logic supply voltage range HV Generator supply range supply current internal VLCD supply current internal VLCD supply current external VLCD supply current external VLCD supply current supply current external VLCD VLCD tolerance internal generated LOW level input voltage HIGH level input voltage LOW level output current (SDA) leakage current Row output resistance R0 to R64 Column output resistance C0 to C101 VOL = 0.4V; VDD1 = 5 V VI = VDD1 or VSS1 -1 12 12 VLCD = 10.0V; fscl = 0; display load = 0; VLCD = 10.0V; fscl = 0; display load = 0; (1)(5) VLCD = 10.0V; fscl = 0; display load = 0; VLCD = 10.0V; fscl = 0; display load = 0; (2)(5) power-down mode; VLCD = 0V; fscl = 0; display load = 0 VLCD = 10 V; fSCL= 0, display load = 0; (2) VDD = 2.7V; VLCD = 10V; fSCL = 0; display load = 0;(3)(4)(6) VSS 0.7 VDD 3.0 +1 20 20 CONDITIONS MIN 1.5 2.4 30 600 30 0 0.5 50 3 TYP 6 5 80 1200 80 10 10 130 MAX UNIT V V A A A A A A
SYMBOL VDD1 VDD2, VDD2_HV IVDD1 IVDD2/2_HV IVDD1 IVDD2/2_HV IVDD1 ILCD VLCD(tol) VIL VIH IOL IL RROW RCOL Note
+/- 500 mV 0.3VDD V VDD V mA A kOhm kOhm
1. When a display is connected the IVDD2_HV increases with 7 x display load current due to 7 stage charge pump. 2. With external VLCD, the display load current does not translate into increased IVDD2_HV. 3. For TC1, TC2 and TC3 4. The maximum possible VLCD voltage that may be generated is dependent on voltage (VDD2/2_HV), temperature and (display) load. 5. VDD2 VDD2_HV connected together 6. Difference to the theoretical value given by equation 1
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Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
AC CHARACTERISTICS Table 8
PCF8549
VDD1 = 1.5 to 6 V; VDD2/2_HV = 2.4 to 5.0 V; VDD2 = VDD2_HV; VSS1 = VSS2 = VSS2_HV = 0 V; VLCD = 7 to 16 V; Tamb = -40 to +85 C; unless otherwise specified. PARAMETER oscillator frequency external clock frequency oscillator start up time frame frequency VDD to RES Low reset low pulse width
(2) (5)
SYMBOL fOSC fEXT tstart fFRAME tVHRL tPWRES
CONDITIONS 19 10 - = 32 kHz;(1) -
MIN.
TYP. 32 32 450 62 - - - - - -
MAX. 64 64 1600 - 1 -
UNIT kHz kHz us Hz ms ns
fEXT (5)
400
I2C timing characteristics fSCLK tLOW tHIGH tSU;Data tHD;Data tR tF cb tSU;STA tHD;STA tSU;DAT tHD;DAT tSU;STO tSW tBUF Note 1. f EXT f FRAME = ---------520 SCL clock frequency SCL clock low period SCL clock high period Data set-up time Data hold time SCL and SDA rise time SCL and SDA fall time Capacitive load represented by each bus line setup time for a repeated START condition start condition hold time data set-up time data hold-time setup time for STOP condition tolerable spike width on bus BUS free time between a STOP and START condition
(4) (3) (3) (6)
DC 1.3 0.6 100 0
400 - - - 0.9 300 300 400 - - - - - 50 -
kHz us us ns us ns ns pF us us ns ns us ns us
20 + 0.1 Cb - 20 + 0.1 Cb - - 0.6 0.6 100 0 0.6 - 1.3 - - - - - - - -
2. Duty cycle of 50 +/-5%. 3. The rise and fall times specified here refer to the driver device (i.e. not PCF8549) and are part of the general fast I2C-bus specification. When PCF8549 asserts an acknowledge on SDA, the minimum fall time is 10ns. Cb= capacitive load per bus line. 4. The device inputs SDA and SCL are filtered and will reject spikes on the bus lines of width < tSW(max). 5. Not tested in production 6. Only for VDD1= 2V to 6V
1997 Nov 21
22
Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
TYPICAL CHARACTERISTICS
PCF8549
16V 15V
I=0uA
VLCD
14V I=10uA
I=20uA
13V
I=40uA
12V 0V 1V 2V 3V 4V 5V
VDD2, VDD2_HV Fig.16 VLCD dependency of VDD2, VDD2_HV and load current. Programmed VLCD=15.8V (@ Room Temperature in special Test mode)
RESET
VDD tVHRL
tPWRES RES
Fig.17 Reset timing.
1997 Nov 21
23
Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
APPLICATION INFORMATION Table 9 STEP DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 2 3 4 I2C start 0 0 0 1 0 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 Slave address for write programming example for PCF8549 DISPLAY OPERATION
PCF8549
Control byte with cleared CO bit and D/C set to 0. Function Set PD = 0; V = 0; select extended instruction set (H = 1 mode) Set Bias System 2. This is the recommended Bias System for a multiplex rate 1:65 set VOP VOP is set to a +16 x b [V]. Please note: The required voltage is depending on the liquid. Function Set PD = 0; V = 0; select normal instruction set (H = 0 mode) Display Control set normal mode (D = 1 and E = 0) Restart: To write into the Display RAM the D/C must be set to 1; therefore a control byte is needed.
5
0
0
0
1
0
0
1
0
6
1
1
1
0
1
0
1
0
7
0
0
1
0
0
0
0
0
8
0
0
0
0
1
1
0
0
9
I2C start
10 11 12
0 0 1
1 1 1
1 0 1
1 0 1
1 0 1
0 0 0
0 0 0
0 0 0
Slave address for write Control byte with cleared CO bit and D/C set to 1. Data Write Y and X are initialized to 0 by default, so they aren't set here Data Write
13
1
0
1
0
0
0
0
0
14
1
1
1
0
0
0
0
0
Data Write
1997 Nov 21
24
Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
PCF8549
STEP DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 15 0 0 0 0 0 0 0 0
DISPLAY
OPERATION Data Write
16
1
1
1
1
1
0
0
0
Data Write
17
0
0
1
0
0
0
0
0
Data Write
18
1
1
1
1
1
0
0
0
Data Write
19 20 21 22
I2C start 0 1 0 1 0 0 1 0 0 1 0 0 1 0 1 0 0 1 0 0 0 0 0 1
Restart Slave address for write Control byte with set CO bit and D/C set to 0. Display Control Set inverse video mode (D = 1 and E = 1) Control byte with set CO bit and D/C set to 0. Set X address of RAM set address to `0000000'
23 24
1 1
0 0
0 0
0 0
0 0
0 0
0 0
0 0
25 26
1 0
1 0
0 0
0 0
0 0
0 0
0 0
0 0
Control byte with set CO bit and D/C set to 1. Data Write
27 28
0 1
0 0
0 0
0 0
0 0
0 0
0 0
0 0
Control byte with cleared CO bit and D/C set to 0. Set X address of RAM Set address to `0000000'
29
0
0
0
0
0
0
0
1
Set Read Modify Write Mode
1997 Nov 21
25
Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
PCF8549
STEP DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 30 31 32 33 34 35 I2C start 0 1 1 1 1 0 1 0 1 0 0 0 0 0 0 0
DISPLAY Restart
OPERATION
Slave address for write Control byte with set CO bit and D/C set to 1. Restart Slave address for read Read Data From Address `0000000'
I2C start 0 1 1 0 1 0 1 0 1 0 0 0 0 0 1 0
36
1
0
0
0
0
0
0
0
Read Data From Address `0000000' again. Master does not send an acknowledge to stop the read access. Restart Slave address for write Control byte with set CO bit and D/C set to 1. Write Data
37 38 39 40
I2C start 0 1 1 1 1 1 1 0 1 1 0 1 1 0 1 0 0 0 0 0 0 0 0 0
41 42 43 44
1
0
0
0
0
0
0
0
Control byte with set CO bit and D/C set to 0. Restart Slave address for read Read Status Byte
I2C start 0 1 1 0 1 0 1 0 1 0 0 0 0 0 1 0
APPLICATION INFORMATION
1997 Nov 21
26
Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
PCF8549
VDD1
SCL
VDD1
SDA SDA_OUT
SDA
Fig.18 Application diagram: Connecting the I2C Interface
1997 Nov 21
27
Microcontroller
SCL
PCF8549
Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
PCF8549
DISPLAY 102x65
33
102
32
PCF8549
13
VDD1 - VSS 1.5V VDD2 - VSS 2.4V VDD2HV = VDD2 C2 C1
I/O
C3
C1 100nF C2 100nF C3 1uF C4 100nF
VDD2 VDD2_HV
Fig.19 Application diagram: Connecting the power supplies
The pinning of the PCF8549 is optimized for single plane wiring e.g. for chip-on-glass display modules. Display size: 65 x 102 pixels. CHIP INFORMATION The PCF8549 is manufactured in n-well CMOS technology. The substrate is on VSS potential.
1997 Nov 21
28
VDD1
C4
VSS
VLCD
Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
BONDING PADS VALUE Pad pitch Passivation. Bumps Wafer thickness min. 100 48 x 78 380 (25) Pad size, alumin. 80 x 100 UNIT m m m m
PCF8549
60 (6) x 90 (6) x 17.5 (5) m
1997 Nov 21
29
Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
PCF8549
Dummy R31
Recognition Pattern
DUMMY R63
R1 OSC VDD1
R33 C0
VDD2
VDD2_HV RES SDA_OUT
SDA
SCL T2 SA0 T7 T6 T5 T4 T3 T1 VSS1 VSS2_HV VSS2 PC8549 C101 R32 R34 Recognition pattern Pad 1
VLCD_1 VLCD2 R0
R30 Dummy
R64 DUMMY
2.74mm
Fig.20 Pads.
1997 Nov 21
30
16.39mm
Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
Table 10 Bonding pad locations (dimensions in um). Pad 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Pad name T2 SA0 T7 T6 T5 T4 T3 T1 VSS1 VSS1 VSS2_HV VSS2_HV VSS2_HV VSS2 VLCD1 VLCD2 ROW<0> ROW<2> ROW<4> ROW<6> ROW<8> ROW<10> ROW<12> ROW<14> ROW<16> ROW<18> ROW<20> ROW<22> ROW<24> ROW<26> ROW<28> ROW<30> Dummy 4 Dummy 5 Dummy 6 Dummy 3 Dummy 2 Dummy 1 ROW<64> ROW<62> X 7359.5 6958 6679 6400 6121 5841.5 5431.5 5022 4724 4624 4359 4259 4159 3458.5 2580 2294 1870 1770 1670 1570 1470 1370 1270 1170 1070 970 870 770 670 570 470 370 270 170 70 70 170 270 370 470 Y 2462 2462 2462 2462 2462 2462 2462 2462 2458 2458 2458 2458 2458 2458 2462 2462 2437 2437 2437 2437 2437 2437 2437 2437 2437 2437 2437 2437 2437 2437 2437 2437 2437 2437 2437 84 84 84 84 84 31 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
PCF8549
Pad
Pad name ROW<60> ROW<58> ROW<56> ROW<54> ROW<52> ROW<50> ROW<48> ROW<46> ROW<44> ROW<42> ROW<40> ROW<38> ROW<36> ROW<34> ROW<32> COL<101> COL<100> COL<99> COL<98> COL<97> COL<96> COL<95> COL<94> COL<93> COL<92> COL<91> COL<90> COL<89> COL<88> COL<87> COL<86> COL<85> COL<84> COL<83> COL<82> COL<81> COL<80> COL<79> COL<78> COL<77>
X 570 670 770 870 970 1070 1170 1270 1370 1470 1570 1670 1770 1870 2137 2812 2914 3014 3114 3214 3314 3560 3660 3760 3860 3960 4060 4160 4260 4360 4460 4560 4660 4760 4860 4960 5060 5306 5406 5506 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84
Y
1997 Nov 21
Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
PCF8549
Pad 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
Pad name COL<76> COL<75> COL<74> COL<73> COL<72> COL<71> COL<70> COL<69> COL<68> COL<67> COL<66> COL<65> COL<64> COL<63> COL<62> COL<61> COL<60> COL<59> COL<58> COL<57> COL<56> COL<55> COL<54> COL<53> COL<52> COL<51> COL<50> COL<49> COL<48> COL<47> COL<46> COL<45> COL<44> COL<43> COL<42> COL<41> COL<40> COL<39> COL<38> COL<37>
X 5606 5706 5806 5906 6006 6106 6206 6306 6406 6506 6606 6706 6806 7052 7152 7252 7352 7452 7552 7652 7752 7852 7952 8052 8152 8252 8352 8452 8552 8798 8898 8998 9098 9198 9298 9398 9498 9598 9698 9798 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84
Y
Pad 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160
Pad name COL<36> COL<35> COL<34> COL<33> COL<32> COL<31> COL<30> COL<29> COL<28> COL<27> COL<26> COL<25> COL<24> COL<23> COL<22> COL<21> COL<20> COL<19> COL<18> COL<17> COL<16> COL<15> COL<14> COL<13> COL<12> COL<11> COL<10> COL<9> COL<8> COL<7> COL<6> COL<5> COL<4> COL<3> COL<2> COL<1> COL<0> ROW<33> ROW<35> ROW<37>
X 9898 9998 10098 10198 10298 10544 10644 10744 10844 10944 11044 11144 11244 11344 11444 11544 11644 11744 11844 11944 12044 12290 12390 12490 12590 12690 12790 12890 12990 13090 13190 13290 13390 13490 13590 13690 13790 14204 14304 14404 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84
Y
1997 Nov 21
32
Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
PCF8549
Pad 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200
Pad name ROW<39> ROW<41> ROW<43> ROW<45> ROW<47> ROW<49> ROW<51> ROW<53> ROW<55> ROW<57> ROW<59> ROW<61> ROW<63> Dummy 7 Dummy 8 Dummy 9 Dummy 12 Dummy 11 Dummy 10 ROW<31> ROW<29> ROW<27> ROW<25> ROW<23> ROW<21> ROW<19> ROW<17> ROW<15> ROW<13> ROW<11> ROW<9> ROW<7> ROW<5> ROW<3> ROW<1> OSC VDD1 VDD1 VDD1 VDD2
X 14504 14604 14704 14804 14904 15004 15104 15204 15304 15404 15504 15604 15704 15804 15904 16004 15961 15861 15761 15661 15561 15461 15361 15261 15161 15061 14961 14861 14761 14661 14561 14461 14361 14261 14161 13738 13147 13047 12947 12145 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84 84
Y
Pad 201 202 203 204 205 206 207 208 209
Pad name
X
Y 2461 2461 2461 2462 2462 2462 2462 2462 2462 2437 80 1824
VDD2_HV_I 11145 N VDD2_HV_I 11045 N VDD2_HV_I 10945 N RES_B_IN SDA_OUT SDA_IN SDA_IN SCL_IN SCL_IN Recpat C1 Recpat C2 Recpat F 10627 10333.5 5 9412.4 9212.4 8256.8 8056.8 16275 2301 304
2437 2437 2437 2437 2437 2437 2437 2437 2437 2437 2437 2437 2437 2437 2437 2437 2437 2437 2437 2462 2461 2461 2461 2461
1997 Nov 21
33
Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
PCF8549
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1997 Nov 21
34
Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
NOTES
PCF8549
1997 Nov 21
35
Philips Semiconductors - a worldwide company
Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 160 1010, Fax. +43 160 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 689 211, Fax. +359 2 689 102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. +45 32 88 2636, Fax. +45 31 57 0044 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615800, Fax. +358 9 61580920 France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex, Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 23 53 60, Fax. +49 40 23 536 300 Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS, Tel. +30 1 4894 339/239, Fax. +30 1 4814 240 Hungary: see Austria India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: see Singapore Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Al. Vicente Pinzon, 173, 6th floor, 04547-130 SAO PAULO, SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 821 2382 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 3 301 6312, Fax. +34 3 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 632 2000, Fax. +46 8 632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2686, Fax. +41 1 481 7730 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777
For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1997
Internet: http://www.semiconductors.philips.com
SCA56
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
417067/1200/01/pp36
Date of release: 1997 Nov 21
Document order number:
9397 750 03044

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